The present invention relates, in general, to data processing systems and in particular to Array Built-In Self Test (ABIST) and improved programmable ABIST for integrated circuit special arrays used to make the processor incorporated in the data processing system.
In general, integrated circuit arrays (e.g., memory arrays) are tested by providing a known data input at a known address to the array and comparing the output to the expected output. One well known and widely used system for testing integrated circuit logic, particularly integrated circuit memory arrays, is to form a dedicated test circuit on the chip with the array itself. This Array Built-In Self Test (ABIST) technology allows high speed testing of the array without having to force correspondence between the array and the input/output connections to the chip itself. In order to provide high speed testing and to confine the test system to a minimum area of the chip, early ABIST systems had hardwired circuits for generation of test data, generation of control sequences, and test data gathering. However changes in the structure and types of arrays in integrated circuit chips required special hardware for each type of array tested and for the varied expected failure conditions. Improvements in ABIST followed when the control sequences and test patterns were generated by a programmable ABIST (PABIST) systems. PABIST systems allowed a programmable controller with an instruction storage space to be loaded with instructions via a level sensitive scan device (LSSD).
A PABIST system tests an array by executing a sequence of instructions to generate test patterns for an array, testing results and scanning out the test results also using a LSSD. With a suitable instruction set, control of how the sequence was executed and incorporating methods for changing instruction sequence, a sophisticated and powerful PABIST was possible. Programmability enabled a standard test system to be integrated onto integrated circuits for testing a variety of array types and variety of failure modes. PABIST also allowed new tests to be developed and used without modifying the hardwired circuits of the integrated circuit chip.
Some arrays in VLSI circuits have imbedded logic functions that are not separable from the array itself. In the past thorough testing of these arrays has not been possible. Incorporating circuits to isolate the imbedded logic functions adds complexity to the special arrays with imbedded logic. Enabling the test of special arrays within VLSI is an important part of a thorough test plan using PABIST especially where it is desirable to multiplex a PABIST for the testing of many internal arrays.
Clearly there is a need to improve the programmable ABIST system to deal with increased array complexity and the complexity of test patterns and sequences needed to test the failure modes of the arrays. It is also important to enable the PABIST system to test arrays with imbedded array logic functions.
Some arrays have imbedded logic on the array output and have a feature that allows multiple addresses to be selected during a read. When multiple addresses are selected during a read, the array output is the logic combination of the selected read addresses. The present invention enables testing of arrays of this type by first testing the array for reads and writes of various data patterns and corresponding sequences of reads and writes where only one address is selected at a time during a read. After the array is tested, a second set of tests is executed where a data patten is initially written to all addresses then subsequently a second data pattern is written to one address and a read is executed with all addresses selected concurrently. The array output data is the logic combination of the data written to one address with the data pattern initially written to all addresses. The expected output for the logic combination is compared to actual array output with all addresses selected concurrently. By writing to all addresses a first data pattern followed by writes of a second data pattern to single addresses, all of the imbedded logic on array outputs may be tested.
The present invention anticipates that special arrays with imbedded logic on array outputs may be read/write functionally tested using an Array Built-In Self-Test (ABIST) method prior to testing of their imbedded logic functions. Different configurations of ABIST may be employed to test an array prior to testing the imbedded logic and still be within the scope of embodiments of the present invention. The read/write functionality of an array with imbedded logic, can be tested with ABIST, programmable ABIST (PABIST) or a PABIST system with a programmable expect generator (PEG).
If the logic on the array outputs, when tested using embodiments of the present invention, does not present outputs that are known as previously written inputs or are not sequentially related to previously written inputs a PEG may be used to generate expected outputs. Those features of the PEG used to test read/write functionality may be used to facilitate, in embodiments of the present invention, testing of imbedded logic functions of special arrays.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention.